1. Field of the Invention
The present invention relates to a thin film transistor and a fabrication method thereof, and in particular to an improved thin film transistor and a fabrication method thereof which are capable of significantly increasing an ON/OFF current ratio.
2. Description of the Conventional Art
FIG. 1 illustrates a conventional top type polycrystalline-silicon thin film transistor.
As shown therein, on a substrate 11, a first oxide film 12 is formed. A polysilicon layer 13 is formed on the first oxide film 12 by a chemical vapor deposition (CVD) method. A second oxide film 14 which is an insulation layer is formed on the polysilicon layer 13. Thereafter, using a mask (not shown), the second oxide film 14 is selectively etched so that the surface of the polysilicon layer 13 is exposed for forming source/drain portions thereon, and then a gate electrode 15 is formed on the second oxide film 14. Impurities such as B ions or P ions are implanted into the surface-exposed polysilicon layer 13 for thus forming the source/drain regions 16 and 17. Thereafter, the source/drain electrodes 18 and 19 which electrically contact with the source/drain regions 16 and 17 are formed, thus finally fabricating the conventional thin film transistor.
In the thin film transistor as shown in FIG. 1, when a higher voltage than the threshold voltage is supplied to the gate electrode 15, and when the voltage of the drain electrode 17 is increased to a voltage higher than the source electrode 16, electrons are transferred from the source 16 to the drain 17 through the channel region, thus generating a driving current. However, in the thin film transistor as shown in FIG. 1, when a channel is formed by applying voltage to the gate, the carrier mobility is degraded by an electric potential barrier formed at grain boundaries inside the polysilicon. Therefore, when the voltage is supplied thereto, the driving current is decreased by the electric potential barrier, so that a leakage current which decreases the ON/OFF current ratio of the drain current is generated due to the above-described problem.
A thin film transistor, which is capable of increasing the ON/OFF current ratio by forming an offset region and decreasing the leakage current, is disclosed in IEEE Electron Device Letters Vol. 9. No 1, January 1988 (Title: Characteristics of offset structure polycrystalline silicon . . . ).
Referring to FIG. 2, the fabrication method of the above-described thin film transistor will now be explained.
First, on a substrate 21, a polysilicon film 22 is deposited by an LPCVD (Low Pressure chemical Vapor Deposition) method. A low density of P-ions are implanted into offset regions 23a and 23b, and a high density of P-ions are implanted into the source/drain regions 24a and 24b. The resultant structure is heat-processed at a temperature of about 900.degree. C. for activating the implanted impurities, and then a gate insulation film 25 formed of SiN is deposited on the polysilicon layer 22. A contact hole is formed in the gate insulation film 25, and an aluminum layer is deposited on the resultant structure. Thereafter, the aluminum layer is etched for thus forming a gate electrode 26, a source electrode 27, and a drain electrode 28. At this time, the offset length Ls is 3 .mu.m through 7 .mu.m.
In the thin film transistor as shown in FIG. 2, the ON/OFF current ratio is increased up to a level higher than that of the thin film transistor as shown in FIG. 1 by the offset regions 23a and 23b. However, the current is disadvantageously decreased in the turn-on mode due to the offset region 23a formed near the source region 24a. In order to overcome the above-described problem, a transistor in which the offset region 23a was not formed near the source region 24a was proposed in the industry. Moreover, the above-described thin film transistor fabrication method has a disadvantage in that an additional masking process step is needed for defining the source/drain regions and the offset region, thus complicating the fabrication process.